1. Field of the Invention
The present invention relates to power-on reset circuits for integrated circuits and, more particularly, to a power-on reset circuit suitable for high density integrated circuits.
2. Description of the Related Art
A power-on reset circuit (sometimes called a power up detection circuit) provides a reset signal for initializing flip-flops, latches, counters, registers and other such internal components of a semiconductor integrated circuit, when power is applied thereto. The reset signal is maintained at a first constant voltage (e.g., a logic low or "0") for a sufficient time to allow stabilization of the respective components of the circuit. After a predetermined time, the reset signal is switched to a second constant voltage e.g., a logic high or "1") for as long as the power is applied to the circuit.
A large variety of power-on reset circuits have been proposed, such as U.S. Pat. No. 4,885,476, by Mahabadi, issued on Dec. 5, 1989, disclosing a power-on reset circuit including a start-up voltage generator circuit which produces a voltage which is insensitive to changes in field effect transistor threshold voltages, in which a reset signal is fed back to the start-up voltage generator circuit to reduce the steady state current.
U.S. Pat. No. 5,386,152, by Naraki, Jan. 31, 1995, discloses a reset signal generating circuit which generates and provides a reset signal for a logic unit during a certain period only when a power component from the output of a differentiator circuit exceeds a threshold voltage of the reset signal generating circuit.
U.S. Pat. No. 5,463,335, by Divakaruni et al., issued on Oct. 31, 1995, teaches a power-on reset circuit which includes an output terminal connected through an impedance to a power supply, with the output terminal being further connected through a subthreshold leakage device for a latch to a point of reference potential, the subthreshold leakage device being switched from an initial subthreshold mode to a conduction mode in response to a predetermined level of output voltage developed on the output terminal.
U.S. Pat. Nos. 5,612,642 and 5,760,624, by McClintock, issued on Mar. 26, 1997 and Jun. 2, 1998, respectively, disclose power-on reset circuits each of which deasserts a power on reset signal until the power supply voltage level drops to a level low enough to render storage elements in a circuit controlled by the reset signal incapable of holding accurate data.
When designing power-on reset circuits, consideration must be given to steady-state power dissipation, chip layout, production costs and the stability of the reset signal. In designing a typical power-on reset circuit, the steady-state power dissipation should be minimized. In addition, to economize the layout area of the chip, the use of passive elements (e.g., capacitors and resistors) which occupy a relatively large area, and depletion mode transistors which add a manufacturing step, should be avoided.
With reference to FIG. 1, there is illustrated a conventional monolithic semiconductor integrated circuit chip with a power-on reset circuit 12, which is disclosed in U.S. Pat. No. 5,376,835, by Van Buskirk et al., issued on Dec. 27, 1994. The power-on reset circuit 12 illustrated in FIG. 1 may be designed so as to be incorporated into a semiconductor chip along with logic and/or memory circuitry 18 and a voltage reference generator 38. The power-on reset circuit 12 provides a reset signal VCCOK on its first output terminal 14 which is coupled vial line 16 to logic and/or memory circuitry 18 containing a state machine having state registers SR1, SR2, . . . , SRn. The reset signal VCCOK is a logic signal which resets the state registers SR1, SR2, . . . , SRn when it is at a low or "0" logic level (active state).
The true outputs Q1 through Qn of the respective registers SR1 through SRn are connected to corresponding inputs of a NOR gate 20 via lines 22a-22n, respectively. The output of the logic gate 20 on line 24 is fed to an inverter gate 26 on line 28 which provides a state monitoring signal SMON which is connected to a first input terminal 32 of the power-on reset circuit 12.
The power-on reset circuit 12 includes a second output terminal 34 which provides a logic control signal VON which is fed via line 35 to an input terminal 36 of the voltage reference generator 38. The voltage reference generator 38 generates a stable reference voltage VREFI on its first output terminal 40 which is fed via line 42 to a second input terminal 44 of the power-on reset circuit 12. The reference generator 38 also provides a start-up voltage VCCDC on its second output terminal 46 which is fed via line 48 to a third input terminal 50 of the power-on reset circuit 12.
The power-on reset circuit 12 operates in response to the monitoring signal SMON, the start-up voltage VCCDV, and the reference voltage VREFI, and generates and maintains the reset signal VCCOK at an active low state during power-up until the power supply voltage exceeds a predetermined level. More specifically, the power-on reset circuit 12 is active during power-up only if one of the outputs of the state registers SR 1-SRn is high (i.e., in the non-reset state). Otherwise, if the outputs of the state registers SR 1-SRn happen to come up in the reset state (all outputs being low), then the power-on reset circuit 12 is never activated at all since the logic control signal VON remains low. When the state registers SR1-SRn are powered up in the non-reset state, the reset signal VCCOK continues to be applied to the reset inputs of the state registers SR 1-SRn until the power supply voltage VCC has reached a predetermined level so as to insure proper operation of the logic and/or memory circuitry 18. Thereafter, the power-on reset circuit 12 shuts itself off in response to the monitoring signal SMON, thereby reducing power consumption.
However, the above-described arrangement, in which the outputs of the state registers SR1-SRn are used for shutting off the power-on reset circuit 12 through logic gates 20 and 24, requires a considerable increase in the layout area for the power-on reset circuit as the number of the state registers increases because the number of logic gates must necessarily increase due to limitations on logic circuit construction such as fan-in. Therefore, the density of an integrated circuit chips having the above-described arrangement is reduced.